So-called BiCMOS ICs which combine bipolar transistors and MOS transistors formed on a same substrate have lately been used in a variety of electronic products, utilizing features of both types of transistors, that is, high speed performance of the bipolar transistors and low power consumption of the MOS transistors. With this situation, there is a gradually increasing need for smaller, higher performance and higher reliability BiCMOS ICs.
A semiconductor device as an example of prior art BiCMOS ICs is shown in FIG. 1, where the semiconductor device 200 comprises a vertical NPN transistor 80, a lateral PNP transistor 85, an NMOS transistor 90, and a PMOS transistor 95, and a semiconductor substrate 99 on which the transistors are formed. They constitute a BiCMOS IC. Hereinafter, “V- ” will be referred to as “vertical” and “L- ” as “lateral.”
As shown in FIG. 1, this semiconductor device 200 includes a P-type silicon substrate 99. Also, the semiconductor device 200 includes an epitaxial layer 84 on the silicon substrate 99. This epitaxial layer 84 is an N-type monocrystalline silicon layer formed by epitaxial growth. An interface between the epitaxial layer 84 and the silicon substrate 99 is indicated by a dotted line in FIG. 1. In the epitaxial layer 84, element isolation regions 89 which are formed from a silicon oxide film are selectively formed. Also, under the element isolation regions 89, element isolation wells 93 which are formed from a P-type impurity diffusion layer are selectively formed at the interface between the epitaxial layer 84 and the silicon substrate 99. The above-mentioned transistors are formed in the areas confined by the element isolation regions 89 and the like.
The V-NPN transistor 80 is formed in the area confined by the element isolation regions 89 and element isolation wells 93 which are the left two ones shown in FIG. 1 on the silicon substrate 99. This V-NPN transistor 80 comprises an N-type emitter region 81, a P-type base region 82, and an N-type collector region 83. Among these regions, the collector region 83 consists of a part of the N-type epitaxial layer 84. The base region 82 is formed within a part of the collector region 83. The emitter region 81 is also formed within a part of the base region 82. The thickness of the base region 82 directly under the emitter region 81 is the base width of the V-NPN transistor 80. This base width of the V-NPN transistor 80 is determined by conditions of ion implantation and thermal process which are performed when forming the base region 82 and the emitter region 81.
As shown in FIG. 1, the L-PNP transistor 85 is formed in the area adjacent to the V-NPN transistor 80 across the element isolation region 89 and element isolation well 93 on the silicon substrate 99. This L-PNP transistor 85 comprises a P-type emitter region 86, an N-type base region 87, and a P-type collector region 88. In the L-PNP transistor 85, the base region 87 consists of a part of the N-type epitaxial layer 84. The collector region 88 and the emitter region 86 are laterally disposed within parts of the base region 87. The gap distance between the emitter region 86 and the collector region 88 is the base width of the L-PNP transistor 85. This base width of the L-PNP transistor 85 is determined by the shape of a mask (resist pattern) which is used when forming the collector region 88 and the emitter region 86.
Besides, the NMOS 90 is formed in the area adjacent to the L-PNP transistor 85 across the element isolation region 89 and element isolation well 93 on the silicon substrate 99. This NMOS 90 comprises a P-type well region 92 which is formed by implanting P-type impurities into the epitaxial layer 84 and a source region 91A and a drain region 91B which are of N type and formed within parts of the P-type well region 92. Besides, the PMOS 95 is formed in the area adjacent to the NMOS 90 across the element isolation region 89 on the silicon substrate 99. This PMOS 95 comprises a well region which consists of a part of the N-type epitaxial layer 84 and a source region 96A and a drain region 96B which are of P type and formed in the epitaxial layer 84.
By the way, according to the conventional semiconductor device 200, the base width of the V-NPN transistor 80 has been determined by the conditions of ion implantation and thermal process performed when forming the base region 82 and the emitter region 81. The base width of the L-PNP transistor 85 has been determined by the shape of the mask used when forming the collector region 88 and the emitter region 86. It is more difficult to control the mask shape than to control the conditions of ion implantation and thermal process. Therefore, the base width of the L-PNP transistor 85 is harder to thin than the base width of the V-NPN transistor 80. With evolution in miniaturization of the semiconductor device 200, a problem has arisen that great difference occurs between the V-NPN transistor 80 and the L-PNP transistor 85 in terms of a current amplification rate hFE, collector current Ic, frequency characteristic fT, and other performance parameters. Unbalance in performance characteristics between these bipolar transistors may lead to a fear of disabling the functionality of the semiconductor device 200 as the IC.
With evolution in miniaturization of the semiconductor device 200, another problem has arisen that a hot carrier phenomenon becomes significant because of a shorter distance between the source region and the drain region in the NMOS 90 and the PMOS 95. As the hot carrier increases, the transistor lifespan is shortened significantly. A further problem has been posed with respect to the following. When electron concentration in the source region is reduced in order to enhance dielectric strength (BVds) between the source region and the drain region, thereby suppressing the above hot carrier phenomenon, resistance (Rds) between the source region and the drain region increases. With the increase in Rds, there occurs a decrease in current (Ids) flowing through the channel between the source region and the drain region.